Time-to-failure tree

Abstract

The reliability analysis of critical systems is often performed using fault tree analysis. Fault trees are analyzed using analytic approaches or Monte Carlo simulation. The usage of the analytic approaches is limited in few models and certain kinds of parameter distributions. In contrast to the analytic approaches, Monte Carlo simulation can be broadly used. However, Monte Carlo simulation is time-consuming because of the intensive computation. In this paper, a new model is presented which is called time-to-failure tree. Static and dynamic fault trees can be easily transformed into time-to-failure trees. In fact, each time-to-failure tree is a digital circuit, which can be synthesized to a field programmable gate array (FPGA). Therefore, Monte Carlo simulation can be significantly accelerated using FPGAs.

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