Key considerations in the development of defect sampling methodologies

Abstract

This paper presents the key factors that need to be considered for building an intelligent defect sampling plan for in-line process monitoring in a wafer fab. The methodology is illustrated through examples based on the real data collected from two AMD fabs. The problem is to find the number of lots and wafers per lot to sample at critical process layers for in-line wafer inspection. The objective is to detect and eliminate the yield-limiting process excursions at a minimum cost. Key considerations in building the optimal sampling plan include: separation of clusters in the in-line defect data for reducing the noise, analysis of variance to explain and model the variations across lots and among wafers within a lot, computation of excursion frequencies and their magnitude and estimation of yield loss using approaches such as kill ratio of different defect types. Other important fab considerations include maturity of process technology, number of devices and the product mix, inspection capacity, and costs.

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