A Formal Methodology for Fault Tree Construction

Abstract

A model is presented for formulating the Boolean failure logic, called the fault tree, for electrical systems from associated schematic diagrams and system-independent component information. The model is developed in detail for electrical systems, while its implication and terminology extend to all fault tree construction. The methodology is verified as formal by fault trees constructed by a computer—with typical execution times for a fault tree with 100 gates on the order of 7 sec (on the UNIVAC 1108 computer).The model, called Synthetic Tree Model, is a synthesis technique for piecing together, with proper editing, a fault tree from system-independent component information beginning with the main failure of interest and proceeding to more basic failures. The resultant fault trees are in conventional format, use conventional symbols, and are, consequently, immediately compatible with existing solution techniques. While Synthetic Tree Model develops the fault tree to the level of primary failures, extensions of the model could handle secondary failures, i.e., failure-related feedback between components.

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