An automated methodology for generating a fault tree

R.C. De Vries

59 citations0/0 files storedIEEE Transactions on Reliability

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Risk and Safety Analysis VLSI and Analog Circuit Testing Engineering and Test Systems

Abstract

The author presents an overview of a methodology for the automated generation of fault trees for electrical/electronic circuits from a representation of a schematic diagram. Existing computer programs for the generation of fault trees are briefly discussed, and their deficiencies are indicated. The approach presented here is quantitative and uses backtracking. It is illustrated by an example. A prototype computer program has been written to implement the methodology for DC circuits.>

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1977Computer-aided Synthesis of Fault-trees 1977Computer aided synthesis of fault-trees

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2002A new algorithm for computer-aided fault tree synthesis 1994Computer assisted fault tree construction: a review of methods and concerns 2008A Novel Methodology For Synthesis Of Fault Trees From Matlab-Simulink Model 1992Computer tools for hazard identification, modelling and analysis 2016Method of Computer-Aided Fault Tree Analysis for High-Reliable and Safety Design

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