Quantifying the benefits of cycle time reduction in semiconductor wafer fabrication

Abstract

In recent years, semiconductor manufacturing has become increasingly complex due to device size reduction. Hence the manufacturing cycle time, also called turn around time (TAT), which is defined as the time required from wafer input through probing test, becomes longer year by year. This renders the delay between the occurrence of process defects and their detection a significant problem. On the other hand, customer demands for faster delivery are increasing as product life cycles are getting shorter. Hence, TAT reduction is important for semiconductor manufacturers not only to satisfy customer requirements, but also to remain competitive in their market. This paper examines the financial benefits of TAT reduction in ramping up a new process using stochastic simulation. Results indicate that reducing TAT in the ramp-up phase is important, and that even small reductions can have significant effects over the life cycle of a process.

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